Title :
A 3-V, 2%-mW multibit current-mode ΣΔ DAC with 100 dB dynamic range
Author :
Hamasaki, Toshihiko ; Shinohara, Yoshiaki ; Terasawa, Hitoshi ; Ochiai, Kou-Ichirou ; Hiraoka, Masaya ; Kanayama, Hideki
Author_Institution :
Burr-Brown Ltd., Atsugi, Japan
fDate :
12/1/1996 12:00:00 AM
Abstract :
The area ratio of analog to digital for mixed-mode chip has been inversely proportional to the process design rule for a given dynamic range objective, in contradiction to the LSI trend. This paper presents a design approach to realize a high degree of size reduction with process design rules for analog circuitry and a signal processing architecture for digital circuitry. A five-level current-mode ΣΔ digital-to-analog converter (DAC) system reveals full scale total harmonic: distortion plus noise (THD+N) of -90 dB and dynamic-range of 100 dB at 3 V (low power of 22 mW). Analog-area down-scaling can be accomplished by this architecture to be 1.09 mm2, using 0.6-μm double-poly double-metal (DPDM) CMOS. For the digital filter, a pipeline instruction sequence with multiplierless architecture also gives small area of 1.98 mm2
Keywords :
CMOS integrated circuits; digital-analogue conversion; integrated circuit layout; mixed analogue-digital integrated circuits; sigma-delta modulation; 0.6 micron; 22 mW; 3 V; analog-area down-scaling; digital filter; digital-to-analog converter; double-poly double-metal CMOS; dynamic range; five-level DAC; mixed-mode chip; multibit current-mode ΣΔ DAC; multiplierless architecture; pipeline instruction sequence; process design rules; sigma-delta DAC; Circuits; Digital signal processing chips; Digital-analog conversion; Dynamic range; Large scale integration; Power harmonic filters; Power system harmonics; Process design; Signal design; Total harmonic distortion;
Journal_Title :
Solid-State Circuits, IEEE Journal of
