Hybrid dynamic/quadratic programming algorithm for interconnect tree optimization

Author

Mo, Yu-Yen ; Chu, Chris

Author_Institution

Dept. of Electr. & Comput. Eng., Iowa State Univ., Ames, IA, USA

Volume

20

Issue

5

fYear

2001

fDate

5/1/2001 12:00:00 AM

Firstpage

680

Lastpage

686

Abstract

We present an algorithm for delay minimization of interconnect trees by simultaneous buffer insertion/sizing and wire sizing in this paper. Both wire widths and buffer sizes are chosen from user-defined discrete sets. Our algorithm integrates the quadratic programming approach for handling a wire branch into the dynamic programming (DP) framework. Our experimental results show that our hybrid dynamic/quadratic programming algorithm is faster, more accurate, and uses considerably less memory than the pure DP approach

Keywords

buffer circuits; circuit CAD; circuit optimisation; dynamic programming; integrated circuit design; integrated circuit interconnections; quadratic programming; trees (mathematics); buffer insertion; buffer sizing; deep submicron integrated circuit design; delay minimization; dynamic programming; hybrid algorithm; interconnect tree optimization; quadratic programming; wire sizing; Capacitance; Copper; Delay; Design optimization; Dielectric materials; Dynamic programming; Integrated circuit interconnections; Minimization; Quadratic programming; Wire;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.920705

Filename

920705