• DocumentCode
    1483981
  • Title

    Handling soft modules in general nonslicing floorplan using Lagrangian relaxation

  • Author

    Young, F.Y. ; Chu, Chris C N ; Luk, W.S. ; Wong, Y.C.

  • Author_Institution
    Dept. of Comput. Sci. & Eng., Chinese Univ. of Hong Kong, China
  • Volume
    20
  • Issue
    5
  • fYear
    2001
  • fDate
    5/1/2001 12:00:00 AM
  • Firstpage
    687
  • Lastpage
    692
  • Abstract
    In the early stage of floorplan design, many modules have large flexibilities in shape (soft modules). Handling soft modules in general nonslicing floorplan is a complicated problem. Many previous works have attempted to tackle this problem using heuristics or numerical methods, but none of them can solve it optimally and efficiently. In this paper, we show how this problem can be solved optimally by geometric programming using the Lagrangian relaxation technique. The resulting Lagrangian relaxation subproblem is so simple that the optimal size of each module can be computed in linear time. We implemented this method in a simulated annealing framework based on the sequence pair representation. The geometric program is invoked in every iteration of the annealing process to compute the optimal size of each module to give the best packing. The execution time is much faster (at least 15 times faster for data sets with more than 50 modules) than that of the most updated previous work by Murata and Kuh (1998). For a benchmark data with 49 modules, we take 3.7 h in total for the whole annealing process using a 600-MHz Pentium III processor while the convex programming approach described by Murata and Koh needs seven days using a 250-MHz DEC Alpha. Our technique will also be applicable to other floorplanning algorithms that use constraint graphs to find module positions in the final packing
  • Keywords
    VLSI; circuit layout CAD; geometric programming; integrated circuit layout; relaxation theory; simulated annealing; Lagrangian relaxation; VLSI design; constraint graph; geometric programming; nonslicing floorplanning algorithm; sequence pair; simulated annealing; soft module; Computational modeling; Computer science; Integrated circuit technology; Lagrangian functions; Optimization methods; Shape; Simulated annealing; Topology; Very large scale integration;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.920707
  • Filename
    920707