A plastic packaged 10 Gb/s BiCMOS clock and data recovering 1:4-demultiplexer with external VCO

Author

Hauenschild, Jürgen ; Dorschky, Claus ; Winkler vonMohrenfels, T. ; Seitz, Roland

Author_Institution

Lucent Technol., Nurnberg, Germany

Volume

31

Issue

12

fYear

1996

fDate

12/1/1996 12:00:00 AM

Firstpage

2056

Lastpage

2059

Abstract

Architecture and realization of a 10 Gb/s clock and data recovering demultiplexer (CDR-DMUX) test chip fabricated in a 0.7-μm single poly, 16-GHz BiCMOS process are described. The first stage of the circuit is a combination of a 1:2 DMUX and a parallel early-late phase detector, both supplied with 5-GHz clocks from an external VCO. The plastic package does not measurably degrade the differential data input reflection. The 2.3×2.3 mm² chip dissipates 450 mW at -3.6 V

Keywords

BiCMOS digital integrated circuits; data communication equipment; demultiplexing equipment; digital communication; integrated circuit packaging; plastic packaging; timing; -3.6 V; 0.7 micron; 10 Gbit/s; 16 GHz; 450 mW; BiCMOS demultiplexer; clock recovering demultiplexer; data recovering demultiplexer; external VCO; parallel early-late phase detector; plastic package; single poly BiCMOS process; BiCMOS integrated circuits; Circuit testing; Clocks; Degradation; Detectors; Phase detection; Plastic packaging; Reflection; Semiconductor device measurement; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.545832

Filename

545832