Title :
An architecture of a matrix-vector multiplier dedicated to video decoding and three-dimensional computer graphics
Author :
Fujishima, Hideyuki ; Takemoto, Yusuke ; Onoye, Takao ; Shirakawa, Isao
Author_Institution :
Dept. of Inf. Syst. Eng., Osaka Univ., Japan
fDate :
3/1/1999 12:00:00 AM
Abstract :
An architecture of a matrix-vector multiplier (MVM) is devised, which is dedicated to MPEG-4 natural/synthetic video decoding. The MVM can perform the matrix-vector multiplication both in the inverse discrete cosine transform (IDCT) and in the geometrical transformation of three-dimensional computer graphics (3-D CG); or, specifically, it can achieve the multiplication of a 4×4 matrix by a four-tuple vector necessary in the one-dimensional IDCT for eight pixels and in the geometrical transformation for a point in a 3-D space. This paper describes a new architecture of this MVM and also shows the implementation result of a functional module composed of four MVMs with the use of 440-k transistors, which can operate at 20 MHz or less
Keywords :
code standards; computer graphics; decoding; digital signal processing chips; discrete cosine transforms; inverse problems; matrix multiplication; multiplying circuits; telecommunication standards; transform coding; video coding; 20 MHz; 3D CG; 3D computer graphics; 3D space; IDCT; MPEG-4 natural/synthetic video decoding; four-tuple vector; functional module; geometrical transformation; inverse discrete cosine transform; matrix-vector multiplier architecture; pixels; three-dimensional computer graphics; transistors; Computer architecture; Computer displays; Computer graphics; Decoding; Discrete cosine transforms; Energy consumption; Information systems; MPEG 4 Standard; Power engineering and energy; Rendering (computer graphics);
Journal_Title :
Circuits and Systems for Video Technology, IEEE Transactions on
