Comments on “A robust single phase clocking for low power, high-speed VLSI applications” [and reply]

For the original article see ibid., vol. 31, no. 2, p. 247-54 (1996). The commenter points out that some of the material in a recent paper by Afghahi has been previously published. He also states that a divide-by-two circuit described therein is clock edge-sensitive rather than frequency dependent, and cannot be understood in terms of connecting two digital latches. In reply the author clarifies some aspects of his paper