DocumentCode :
1484811
Title :
Design considerations for databus charge recovery
Author :
Bishop, Benjamin ; Lyuboslavsky, Victor ; Vijaykrishnan, N. ; Irwin, Mary Jane
Author_Institution :
Georgia Univ., Athens, GA, USA
Volume :
9
Issue :
1
fYear :
2001
Firstpage :
104
Lastpage :
106
Abstract :
The charge recovery databus is a scheme which reduces energy consumption through the application of adiabatic circuit techniques. Previous work gives a solid theoretical analysis of this scheme, including quantitative data assuming random bus values. We extend this earlier work by presenting a quantitative analysis of the charge recovery databus using 15 benchmarks and four high level bus coding schemes. We show that a very simple implementation of the charge recovery databus is capable of reducing average energy consumption by 28% beyond traditional high-level bus encoding techniques. In addition, we examine delay and energy consumption in the added hardware.
Keywords :
low-power electronics; system buses; adiabatic circuit; charge recovery databus; delay; energy consumption; high-level bus coding; low-power design; Capacitance; Charge transfer; Circuits; Decoding; Energy consumption; Hardware; Image coding; Pulse modulation; Solids; Voltage;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.920824
Filename :
920824
Link To Document :
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