Distributed LC Resonant Clock Grid Synthesis

Clock distribution networks can consume 35-70% of total chip power in high-performance designs. Resonant clocks can potentially reduce this power by recycling the energy using on-chip inductors. We propose the first automated algorithm called Resonant clOCK Synthesis (ROCKS) that includes distributed LC tank placement, a novel AC-based resonant grid buffer sizing, and resonant grid buffer incremental placement optimization. Experimental results show that using inductors limited to 30% of one metal layer, the resonant clock power can be reduced at least by 40% and the clock buffer area is reduced by at least 53% on average. With larger inductors, it is feasible to achieve up to 90% power savings.