DocumentCode :
1485168
Title :
Generation of high quality tests for robustly untestable path delay faults
Author :
Cheng, Kwang-Ting ; Krstic, Angela ; Chen, Hsi-Chuan
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Volume :
45
Issue :
12
fYear :
1996
fDate :
12/1/1996 12:00:00 AM
Firstpage :
1379
Lastpage :
1392
Abstract :
In many designs a large portion of path delay faults is not robustly testable. In this paper, we investigate testing strategies for robustly untestable faults. We show that the quality of nonrobust tests may be very poor in detecting small defects caused by manufacturing process variation. We demonstrate that better quality nonrobust tests can be obtained by including timing information into the process of test generation. A good nonrobust test can tolerate larger timing variations on the off-inputs. We also show that not all nonrobustly untestable path delay faults may be ignored in high quality delay testing. Functional sensitizable paths are nonrobustly untestable but, under some faulty conditions, may degrade the performance of the circuit. However, up till now, there was no strategy for generating tests for such faults. In this paper, we present algorithms for generating high quality nonrobust and functional sensitizable tests. We also devise an algorithm for generating tests for validatable nonrobust faults which have a high quality in detecting defects but are hard to be generated automatically. Our experimental results show that the quality of delay testing increases if validatable and high quality nonrobust tests, as well as tests for functional sensitizable path delay faults are included
Keywords :
delays; integrated logic circuits; logic testing; VLS1 testing; automatic test generation; delay testing; high quality tests; path delay faults; robustly untestable path delay faults; sensitizable tests; test generation; timing defects; Automatic testing; Circuit faults; Circuit testing; Degradation; Delay; Electrical fault detection; Fault detection; Manufacturing processes; Robustness; Timing;
fLanguage :
English
Journal_Title :
Computers, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9340
Type :
jour
DOI :
10.1109/12.545968
Filename :
545968
Link To Document :
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