High-speed noise-immune AlGaAs/GaAs HBT logic for static memory application

The authors evaluate the performance of a new gate topology that gives large logic swings and a high noise margin at low power dissipation. The measured noise margin (43% of the 3-V logic swing) and transfer characteristics for a hybrid inverter using an AlGaAs/GaAs heterojunction bipolar transistor (HBT) are presented along with simulated data for an integrated device. These simulations lead to a modified structure demonstrating substantially improved transient response and reduced power dissipation (23 ps and 2.1 mW) while maintaining a large noise margin (45% of the 3-V logic swing). Its performance compares favorably with that of emitter coupled logic (ECL)