Title :
Switching activity evaluation of CMOS digital circuits using logic timing simulation
Author :
Juan-Chico, J. ; Bellido, M.J. ; Ruiz-de-Clavijo, P. ; Baena, C. ; Jiménez, C.J. ; Valencia, M.
Author_Institution :
Dept. de Diseno Digital, Centro Nacional de Microelectronica Edificio CICA, Seville, Spain
fDate :
4/26/2001 12:00:00 AM
Abstract :
The degradation delay model is applied to accurately estimate the switching activity in CMOS digital circuits. The model overcomes the limitations of conventional gate-level logic simulators to handle the propagation of glitches, a main source of switching activity. Model results of a four-bit multiplier are within 4% with respect to HSPICE, while Verilog overestimations are up to 68%
Keywords :
CMOS digital integrated circuits; circuit simulation; delay estimation; logic simulation; multiplying circuits; switching; timing; CMOS digital circuits; degradation delay model; four-bit multiplier; glitch propagation; logic timing simulation; switching activity evaluation;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20010389
