Title :
Single-electron memory for giga-to-tera bit storage
Author :
Yano, Kazuo ; Ishii, Tomoyuki ; Sano, Toshiaki ; Mine, Toshiyuki ; Murai, Fumio ; Hashimoto, Takashi ; Kobayashi, Takashi ; Kure, Tokuo ; Seki, Koichi
Author_Institution :
Central Res. Lab., Hitachi Ltd., Tokyo, Japan
fDate :
4/1/1999 12:00:00 AM
Abstract :
Starting with a brief review on the single-electron memory and its significance among various single-electron devices, this paper addresses the key issues which one inevitably encounters when one tries to achieve giga-to-tera bit memory integration. Among the issues discussed are: room-temperature operation; memory-cell architecture; sensing scheme; cell-design guideline; use of nanocrystalline silicon versus lithography; array architecture; device-to-device variations; read/write error rate; and CMOS/single-electron-memory hybrid integration and its positioning among various memory architectures
Keywords :
Coulomb blockade; integrated memory circuits; nanotechnology; quantum interference devices; reviews; silicon; CMOS/single-electron-memory hybrid integration; Si; array architecture; cell-design guideline; device-to-device variations; giga-to-tera bit memory integration; memory-cell architecture; nanocrystalline Si; nanolithography; read/write error rate; room-temperature operation; sensing scheme; single-electron memory; Associate members; CMOS technology; Circuits; Electrodes; Electronic switching systems; Guidelines; Large scale integration; Quantum dots; Single electron devices; Single electron memory;
Journal_Title :
Proceedings of the IEEE
