High-performance subquarter-micrometer gate CMOS technology

Author

Okazaki, Y. ; Kobayashi, Toshio ; Miyake, M. ; Matsuda, T. ; Sakuma, K. ; Kawai, Y. ; Takahashi, M. ; Kanisawa, K.

Author_Institution

NTT, Kanagawa, Japan

Volume

11

Issue

4

fYear

1990

fDate

4/1/1990 12:00:00 AM

Firstpage

134

Lastpage

136

Abstract

A single phosphorous-doped poly(n/sup +/)-Si gate, a 3.5-nm-thick gate oxide, and a retrograde twin-well structure with trench isolation are used in the devices considered. Latchup holding voltages exceed 8 V. The transconductances of 0.22- mu m-gate-length n and p MOSFETs are 450 and 330 mS/mm, respectively, and unloaded ring oscillator delays are 36 ps at 2 V. A static-type 1/2 divider utilizing nMOSFETs of 0.16- mu m gate length and pMOSFETs of 0.22- mu m gate length achieved a maximum operating frequency of 1.3 GHz and power of 5.6 mW at a supply voltage of 2 V.<>

Keywords

CMOS integrated circuits; integrated circuit technology; 0.16 micron; 0.22 micron; 1.3 GHz; 2 V; 330 mS; 450 mS; 5.6 mW; 8 V; CMOS technology; MOSFETs; P doped n/sup +/ polycrystalline Si; Si:P; latchup holding voltages; n-channel devices; p-channel devices; poly-Si gate; retrograde twin-well structure; static-type 1/2 divider; submicron gate length; subquarter-micrometer gate; transconductances; trench isolation; Boron; CMOS technology; Delay; Electrodes; Ion implantation; Isolation technology; MOSFET circuits; Process design; Ring oscillators; Voltage-controlled oscillators;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.61787

Filename

61787