DocumentCode :
1485759
Title :
On the Enhancement of the Drain Current in Indium-Rich InGaAs Surface-Channel MOSFETs
Author :
Sarwar, A. T M Golam ; Siddiqui, Mahmudur R. ; Satter, Md Mahbub ; Haque, Anisul
Author_Institution :
Dept. of Electr. & Electron. Eng., United Int. Univ., Dhaka, Bangladesh
Volume :
59
Issue :
6
fYear :
2012
fDate :
6/1/2012 12:00:00 AM
Firstpage :
1653
Lastpage :
1660
Abstract :
The effects of interface-trap states (Dit) and the shift of the charge neutrality level (CNL) on the enhancement of the drain current in In-rich surface-channel enhancement-mode n-type InGaAs MOSFETs are investigated. In addition to the increase in the bulk mobility, the shift of the CNL toward the conduction band together with high densities of Dit is responsible for the experimentally observed remarkable enhancement of the on-state drain current with increasing In content in the channel. However, when Dit is low, current enhancement is weak, and the location of the CNL has little effect on the current enhancement. Acceptor-type interface-trap states above the conduction-band minima (CBM) play an important role in determining the inversion-layer electron mobility. Representing Dit distribution above the CBM by a constant equal to the Dit value at the CNL causes an overestimation of the drain current at higher gate voltages. It is also observed that the extraction of Dit from the low-frequency gate C-V data is independent of the location of the CNL. We further show that the subthreshold slope (SS) is doubled due to Dit. However, the location of the CNL or the magnitude of Dit above the CBM has little effect on the SS.
Keywords :
MOSFET; electron mobility; gallium arsenide; indium compounds; interface states; CBM; CNL; InGaAs; ON-state drain current; SS; acceptor-type interface-trap states; bulk mobility; charge neutrality level; conduction-band minima; current enhancement; indium-rich surface-channel enhancement-mode n-type MOSFET; interface-trap states; inversion-layer electron mobility; low-frequency gate C-V data; subthreshold slope; Degradation; Dielectrics; Electron mobility; Indium gallium arsenide; Logic gates; MOSFETs; Charge neutrality level (CNL); InGaAs metal–oxide–semiconductor field-effect transistors (MOSFETs); drain-current enhancement; interface-trap states $(D_{rm it})$; subthreshold slope (SS);
fLanguage :
English
Journal_Title :
Electron Devices, IEEE Transactions on
Publisher :
ieee
ISSN :
0018-9383
Type :
jour
DOI :
10.1109/TED.2012.2189863
Filename :
6178784
Link To Document :
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