Synchronization and slip performance in a digital network

The timing of signals and processes within integrated digital networks requires careful control in order to minimize signal degradation through the occurrence of slip. The paper discusses the slip mechanism and the alternative methods of its minimization, i.e. the use of high accuracy clocks working in a plesiochronous mode or the phase locking of nodal clocks to a reference clock. The progress of relevant international standardization activities in CCITT is discussed, particularly in relation to the specification of reference clocks, limits for tolerable slip performance and equipment design limits to cater for wander and jitter in the network. The approach taken to timing control within the international network and to synchronization techniques adopted by certain administrations with respect to synchronization methodology and network topology, clock configurations and interconnecting timing links are also given.