Functional implementation techniques for CPU cache memories

Author

Peir, Jih-Kwon ; Hsu, Windsor W. ; Smith, Alan Jay

Author_Institution

Dept. of Comput. & Inf. Sci., Florida Univ., Gainesville, FL, USA

Volume

48

Issue

2

fYear

1999

fDate

2/1/1999 12:00:00 AM

Firstpage

100

Lastpage

110

Abstract

As the performance gap between processors and main memory continues to widen, increasingly aggressive implementations of cache memories are needed to bridge the gap. In this paper, we consider some of the issues that are involved in the implementation of highly optimized cache memories and survey the techniques that can be used to help achieve the increasingly stringent design targets and constraints of modern processors. In particular, we consider techniques that enable the cache to be accessed quickly and still achieve a good hit ratio. We also consider issues such as area cost and bandwidth requirements. Trace-driven simulations of a TPC-C-like workload and selected applications from the SPEC95 benchmark suite are used in the paper to compare the performance of some of the techniques

Keywords

cache storage; memory architecture; performance evaluation; CPU cache memories; address translation; cache access mechanism; cache area and bandwidth; cache memories; cache memory; design targets; good hit ratio; optimized cache memories; trace-driven simulations; Associative memory; Bandwidth; Bridges; Cache memory; Central Processing Unit; Clocks; Constraint optimization; Costs; Design optimization; Information retrieval;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.752651

Filename

752651