Title :
MetaWire: Using FPGA configuration circuitry to emulate a network-on-chip
Author :
Shelburne, M. ; Patterson, Cameron ; Athanas, Peter ; Jones, Maxwell ; Martin, Benoit ; Fong, R.
Author_Institution :
Bradley Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA, USA
fDate :
5/1/2010 12:00:00 AM
Abstract :
Although there have been many reported implementations of networks-on-chip (NoCs) on FPGAs, they have not seen the same acceptance as NoCs on ASICs. One reason is that communication on a field programmable gate array (FPGA) is already costly because of the die resources and time delays inherent in the reconfigurable structure. Layering another general-purpose network on top of the reconfigurable network simply incurs too many performance penalties. There is, however, already a largely unused, global network available in FPGAs. As a proof-of-concept, we demonstrate that the Xilinx FPGA configuration circuitry, which is normally idle during system operation, can function as a relatively high-performance NoC. MetaWire performs transfers through an overclocked Virtex-4 internal configuration access port and is shown to provide a bandwidth exceeding 200 MB/s.
Keywords :
application specific integrated circuits; delays; field programmable gate arrays; network-on-chip; ASIC; MetaWire; Virtex-4 internal configuration access port; Xilinx FPGA configuration circuitry; field programmable gate array; general purpose network; global network; high performance NoC; network-on-chip; proof-of-concept; reconfigurable network structure; time delays;
Journal_Title :
Computers & Digital Techniques, IET
DOI :
10.1049/iet-cdt.2009.0009