Laser simulation of single-event upset in a p-well CMOS counter

Author

Mazer, Jeffrey A. ; Kang, Keith ; Buchner, Stephen

Author_Institution

Martin Marietta Lab., Baltimore, MD, USA

Volume

36

Issue

1

fYear

1989

fDate

2/1/1989 12:00:00 AM

Firstpage

1330

Lastpage

1332

Abstract

A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.

Keywords

CMOS integrated circuits; counting circuits; integrated logic circuits; radiation hardening (electronics); SEU; laser illumination method; logic circuit; maximum hardness; p-well CMOS counter; pulsed laser technique; single-event upset; supply voltage; wafer-level hardness assurance; CMOS logic circuits; CMOS memory circuits; Circuit simulation; Counting circuits; Lighting; Logic circuits; Read-write memory; SRAM chips; Single event upset; Voltage;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.1989.574133

Filename

574133