Laser simulation of single-event upset in a p-well CMOS counter

A laser illumination method was used to simulate single-event upset (SEU) in a p-well complementary metal-oxide-semiconductor (CMOS) logic circuit. It was found that, unlike the case of the static random access memory (RAM), the sensitivity of a logic circuit to SEU is not necessarily linearly dependent on the supply voltage and that its maximum hardness is achieved at the lower end of the voltage operating range. It is concluded that even though its greatest potential lies in the area of wafer-level hardness assurance the pulsed laser technique can also be used to assess changes in circuit design that have been implemented to increase SEU hardness.