Parasitic Capacitances: Analytical Models and Impact on Circuit-Level Performance

Author

Wei, Lan ; Boeuf, Frédéric ; Skotnicki, Thomas ; Wong, H. -S Philip

Author_Institution

Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA

Volume

58

Issue

5

fYear

2011

fDate

5/1/2011 12:00:00 AM

Firstpage

1361

Lastpage

1370

Abstract

Parasitic capacitances have become a main issue for advanced technology nodes. In this paper, we develop analytical models for parasitic capacitance components for several device structures, including bulk devices, fully depleted silicon-on-insulator devices, and double-gate devices. With these models, we analyze the impact of parasitic capacitances on the circuit-level performance for logic applications. Si complementary metal-oxide-semiconductor roadmap projection is revisited beyond 32-nm technology, with different device design scenarios examined.

Keywords

CMOS integrated circuits; silicon-on-insulator; Si complementary metal-oxide-semiconductor roadmap projection; analytical model; bulk devices; circuit-level performance; device design scenario; device structures; double-gate devices; fully depleted silicon-on-insulator devices; logic application; parasitic capacitance component; Analytical models; Capacitance; Delay; Junctions; Logic gates; Semiconductor device modeling; Silicon; Bulk; circuit-level performance; complementary metal–oxide–semiconductor (CMOS); double gate (DG); fully depleted silicon-on-insulator (FDSOI); parasitic capacitances;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/TED.2011.2121912

Filename

5741718