A Digital Implementation of a Dual-Path Time-to-Time Integrator

This paper presents an asynchronous digital technique for the realization of an integrator that takes as input the time-difference between two rising edges of digital signals and produces a corresponding time-difference output signal. The key element of this circuit is a time-memory cell called TLatch. This circuit has the ability to store the time-difference between two edges and allow its retrieval at a later time. By using two TLatches in parallel, a dual-path high-throughput integrator is proposed. Internal mismatches in delays can be removed using a simple calibration algorithm that aligns the frequency of two internal oscillators, thereby eliminating the need for trimming or any reference element. The proposed architecture is fabricated in 1.2 V 0.13-μm IBM CMOS technology and the experimental results confirm the integration operation.