Newly developed ultra thin fan-out wafer level package for PoP usage

Author

Shimamoto, H. ; Soga, K. ; Takemra, K. ; Yanagisawa, H. ; Asai, Satoshi ; Kondo, K. ; Sugo, M. ; Kato, Haruhisa ; Matsuda, Yuuki

Author_Institution

Wave Technol. Inc., Kawanishi, Japan

fYear

2014

fDate

23-25 April 2014

Firstpage

30

Lastpage

33

Abstract

The limitation of the package height in the smartphone becomes severer and severer. Especially in the case of application processer, TSV structure is necessary to clear 1mm package height that is stacked by 2-4 DRAMs inside. But not only the cost of fabricating Through Si Via (TSV) on the Si device is expensive, also handling of the thin chip is fragile. To solve these problems, we have developed ultra thin fan-out type wafer level package (UT-FOWLP) whose thickness is less than 100um. Using this WLP as Package-on-Package (PoP) stacked on System on a Chip (SOC), the total package height of application processor becomes thinner.

Keywords

DRAM chips; elemental semiconductors; silicon; smart phones; system-on-chip; three-dimensional integrated circuits; wafer level packaging; DRAM; PoP usage; SOC; Si; TSV structure; Through Si Via; UT-FOWLP; application processor; package-on-package; size 1 mm; smartphone; system on a chip; thin chip; ultra thin fan-out type wafer level package; Bonding; Random access memory; Routing; Silicon; System-on-chip; Through-silicon vias; PoP; assembly challenges and solutions; emerging materials and processes for 3D; wafer level packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Packaging (ICEP), 2014 International Conference on

Conference_Location

Toyama

Print_ISBN

978-4-904090-10-7

Type

conf

DOI

10.1109/ICEP.2014.6826655

Filename

6826655