Title :
Nostradamus: a floorplanner of uncertain designs
Author :
Bazargan, Kiarash ; Kim, Samjung ; Sarrafzadeh, Majid
Author_Institution :
Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
fDate :
4/1/1999 12:00:00 AM
Abstract :
Floorplanning is an early phase in chip planning. It provides information on approximate area, delay, power, and other performance measures. Careful floorplanning is, thus, of extreme importance. In many applications, while a good floorplan is needed, the information about all modules is not available, or even worse, part of the provided information is inaccurate. Examples of such applications are designing a huge system where the floorplan is needed early in the design process, but not all the modules have been designed. Another example is the field of reconfigurable computing where it is not known what modules will be needed on the reconfigurable chip as the program is being executed. Floorplanning with uncertainty is the problem of obtaining a good floorplan when the information about module dimensions is not complete. In this paper, the floorplanning problem with uncertainty is formulated. Correlation between input characteristics and output characteristics is studied. Also, it is established that traditional floorplanners are incapable of efficiently handling uncertainty. An effective method for dealing with uncertain data is proposed. Experiments show that, for example, with up to 30% input uncertainty an area estimate with less than 7% error can be obtained
Keywords :
VLSI; circuit layout CAD; delays; integrated circuit layout; modules; network routing; Nostradamus; VLSI; approximate area; chip planning; delay; design process; floorplanner; input characteristics; modules; output characteristics; reconfigurable computing; uncertain designs; Area measurement; Circuits; Delay; Design automation; Design engineering; Power measurement; Process design; Routing; Semiconductor device measurement; Uncertainty;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on