Author :
Dutt, Shantanu ; Arslan, Hasan ; Theny, Halim
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Illinois Univ., Chicago, IL, USA
Abstract :
A probability-based partitioning algorithm, PROP, was introduced in [8] that achieved large improvements over traditional “deterministic” iterative-improvement techniques like Fidducia-Mattheyses (FM) and Krishnamurthy´s look-ahead (LA) algorithm. While PROP´s gain function has a greater futuristic component than PM or LA, it incorporates spatially local information-only information on the removal probabilities of adjacent nets of a cell is used in its gain computation. This prevents a higher-level view of nonlocal structures. Also, giving uniform weights to all nets, results in an inability to differentiate between the futuristic benefit of removing one net from another. This paper investigates for the first time the issues of using nonlocal structural information in gain functions and variable net weights based on the futuristic (stochastic) benefit of moving them from the cutset. The result is a more sophisticated partitioner DEEP-PROP that performs better for circuits with large complexities by incorporating more nonlocal (second order) structural information than PROP. The second-order information is incorporated into cell gains as well as variable net weights-the latter helps to focus future cell moves in the “right” cluster around the currently moved cell and, thus, better utilizes the information that led to its selection as the best move. A lower complexity version, variable weight PROP (VAR-PROP), that also uses dynamically assigned variable net weights, but based on first-order information, has also been developed. Both versions yield significant improvements over PROP on the ACM/SIGDA benchmark suite. DEEP-PROP yields mincut improvements of as much as 39% and an average of 20% for large circuits (10-K to 25-K cells) and an average of 14% over all circuits. DEEP PROP is about a factor of 2.8 times slower than PROP, which is very fast. VAR-PROP, which has a much lower computational complexity than DEEP-PROP, yields for large circuits, maximum and average mincut improvements over PROP of 27% and 18%, respectively, and an average of 12.6% improvement over all circuits. It is only about 14% slower than PROP, For the only very large circuit golem3 in the suite (>100 K cells), the improvements produced by DEEP-PROP and VAR-PROP over PROP are 15.6% and 11.5%, respectively. We also compare DEEP-PROP to FM, PROP and hMetis for a subset of the newer 1SPD98 benchmark circuits, and demonstrate significant improvements over FM and PROP, and comparable mincuts (within 2%) to hMetis, one of the best multilevel partitioners
Keywords :
VLSI; circuit layout CAD; computational complexity; integrated circuit layout; iterative methods; logic partitioning; stochastic processes; ACM/SIGDA benchmark suite; ISPD98 benchmark circuits; PROP; VAR-PROP; VLSI; adjacent nets; computational complexity; dynamically assigned variable net weights; gain computation; gain functions; mincut improvements; multilevel partitioners; nonlocal structures; probability-based partitioning algorithm; removal probabilities; second-order information; spatially local information; stochastic-gain functions; uniform weights; variable net weights; Application software; Circuit testing; Computational complexity; Gain; Iterative algorithms; Large scale integration; Optimization methods; Partitioning algorithms; Stochastic processes; Very large scale integration;