Title :
A timing-driven soft-macro placement and resynthesis method in interaction with chip floorplanning
Author :
Su, Hsiao-Pin ; Wu, Allen C H ; Lin, Youn-Long
Author_Institution :
Dept. of Comput. Sci., Tsinghua Univ., Beijing, China
fDate :
4/1/1999 12:00:00 AM
Abstract :
In this paper, we present a complete chip design method which incorporates a soft-macro placement and resynthesis method in interaction with chip floorplanning for area and timing improvements. We present a performance-driven soft-macro clustering and placement method which preserves hardware descriptive language (HDL) design hierarchy to guide the soft-macro placement process. We develop a timing-driven design flow to exploit the interaction between HDL synthesis and physical design tasks. During each design iteration, we resynthesize soft macros with either a relaxed or a tightened timing constraint which is guided by the post-layout timing information. The goal is to produce area-efficient designs while satisfying the timing constraints. Experiments on a number of industrial designs ranging from 75-K to 230-K gates demonstrate that the proposed soft-macro clustering and placement method improves critical-path delays on an average of 22%. Furthermore, the results show that by effectively relaxing the timing constraint of noncritical modules and tightening the timing constraint of critical modules, a design can achieve 11% to 30% timing improvements with little to no increase in chip area
Keywords :
circuit layout CAD; delays; hardware description languages; integrated circuit layout; iterative methods; timing; HDL synthesis; area-efficient designs; chip area; chip floorplanning; critical modules; critical-path delays; design iteration; hardware descriptive language; noncritical modules; physical design tasks; post-layout timing information; resynthesis method; timing-driven soft-macro placement; Chip scale packaging; Delay; Design methodology; Geometry; Hardware design languages; Integrated circuit synthesis; Routing; Software systems; Time to market; Timing;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on