Title :
Decentralized and Passive Model Order Reduction of Linear Networks With Massive Ports
Author :
Yan, Boyuan ; Tan, Sheldon X -D ; Zhou, Lingfei ; Chen, Jie ; Shen, Ruijing
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas A&M Univ., College Station, TX, USA
fDate :
5/1/2012 12:00:00 AM
Abstract :
It is well known that model order reduction for circuits with many terminals remains a challenging problem. One reason is that existing approaches are based on a centralized framework, in which each input-output pair is implicitly assumed to be equally interacted and the matrix-valued transfer function is assumed to be fully populated. In this paper, we attempt to address this long-standing problem using a decentralized model order reduction scheme, in which a multi-input multi-output system is decoupled into a number of subsystems and each subsystem corresponds to one output and several dominant inputs. The decoupling process is based on the relative gain array, which measures the degree of interaction of each input-output pair. For each decoupled subsystem, passive reduction can be easily achieved using existing reduction techniques. The proposed method is suitable for resistance-dominant interconnects such as on-chip power grids, substrate planes where extremely compact models can be obtained. Simulation results demonstrate the advantage of the proposed method compared to the existing approaches.
Keywords :
MIMO systems; passive networks; transfer function matrices; decentralized model order reduction scheme; decoupling processing; input-output pair; linear network; massive port; matrix-valued transfer function; multiinput multioutput system; on-chip power grid; passive model order reduction scheme; relative gain array; resistance-dominant interconnection; substrate plane; Arrays; Computational modeling; Input variables; Integrated circuit interconnections; Integrated circuit modeling; MIMO; Transfer functions; Decentralized; model order reduction; multi-port networks;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
DOI :
10.1109/TVLSI.2011.2126612