• DocumentCode
    1487886
  • Title

    First-level trigger processor for the ZEUS calorimeter

  • Author

    Dawson, John W. ; Talaga, Richard L. ; Burr, Geoffrey W. ; Laird, Robert J. ; Smith, Wesley ; Lackey, Joseph

  • Author_Institution
    Argonne Nat. Lab., IL, USA
  • Volume
    37
  • Issue
    6
  • fYear
    1990
  • fDate
    12/1/1990 12:00:00 AM
  • Firstpage
    2198
  • Lastpage
    2202
  • Abstract
    The design of the first-level trigger processor for the ZEUS calorimeter is discussed. This processor accepts data from the 13000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at a HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100 K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and it operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flow into the processor at a rate of 5.2 GB/s, and processed data flow from the processor to the global first-level trigger at a rate of 700 MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor.
  • Keywords
    CMOS integrated circuits; calorimeters; emitter-coupled logic; integrated logic circuits; logic arrays; physics computing; trigger circuits; 1 mus; CMOS discrete devices; VME environment; ZEUS calorimeter; emitter-coupled logic; first-level trigger processor; pipelined hardware; programmable gate arrays; registers; tables; CMOS logic circuits; Clocks; Electromagnetic compatibility; Hardware; Logic devices; Photomultipliers; Poles and towers; Programmable logic arrays; Registers; Sampling methods;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.1990.574214
  • Filename
    574214