DocumentCode
1488506
Title
Design and test of large embedded memories: An overview
Author
Rajsuman, Rochit
Author_Institution
Advantest America R&D Centre, Santa Clara, CA, USA
Volume
18
Issue
3
fYear
2001
fDate
5/1/2001 12:00:00 AM
Firstpage
16
Lastpage
27
Abstract
Large on-chip memories are desirable but difficult to implement. Challenges range from design automation to fabrication to test algorithms and memory redundancy and repair
Keywords
electronic design automation; integrated circuit testing; integrated memory circuits; design and test; embedded memories; memory redundancy; on-chip memories; test algorithms; Capacitors; Conductors; Design automation; Dielectrics; Fabrication; Logic; Manufacturing processes; Random access memory; Semiconductor device manufacture; Testing;
fLanguage
English
Journal_Title
Design & Test of Computers, IEEE
Publisher
ieee
ISSN
0740-7475
Type
jour
DOI
10.1109/54.922800
Filename
922800
Link To Document