• DocumentCode
    1488541
  • Title

    System-on-chip testability using LSSD scan structures

  • Author

    Zarrineh, Kamran ; Upadhyaya, Shambhu J. ; Chickermane, Vivek

  • Author_Institution
    Sun Microelectron., Chelmsford, MA, USA
  • Volume
    18
  • Issue
    3
  • fYear
    2001
  • fDate
    5/1/2001 12:00:00 AM
  • Firstpage
    83
  • Lastpage
    97
  • Abstract
    A technology-independent test synthesis tool extends the basic level-sensitive scan design (LSSD) boundary scan methodology. It reuses functional storage elements wherever possible and introduces minimal test logic overhead and delay
  • Keywords
    boundary scan testing; integrated circuit testing; LSSD scan structures; boundary scan; level-sensitive scan design; storage elements; technology-independent; test synthesis tool; Automatic testing; Clocks; Flip-flops; Logic testing; Master-slave; Microelectronics; Protocols; Shift registers; System testing; System-on-a-chip;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.922805
  • Filename
    922805
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1488541