• DocumentCode
    1488556
  • Title

    Automatic generation of parallel CRC circuits

  • Author

    Sprachmann, Michael

  • Author_Institution
    Dependable Comput. Syst., Wien, Austria
  • Volume
    18
  • Issue
    3
  • fYear
    2001
  • Firstpage
    108
  • Lastpage
    114
  • Abstract
    A parallel CRC circuit simultaneously processes multiple data bits. A generic VHDL description of parallel CRC circuits lets designers synthesize CRC circuits for any generator polynomial or required amount of parallelism.
  • Keywords
    data communication; error detection; hardware description languages; logic design; automatic generation; generator polynomial; generic VHDL description; multiple data bits; parallel CRC circuits; Automatic logic units; Circuit synthesis; Circuit testing; Cyclic redundancy check; Decoding; Encoding; Logic circuits; Parallel processing; Polynomials; System testing;
  • fLanguage
    English
  • Journal_Title
    Design & Test of Computers, IEEE
  • Publisher
    ieee
  • ISSN
    0740-7475
  • Type

    jour

  • DOI
    10.1109/54.922807
  • Filename
    922807
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1488556