An eighth-order bandpass ΔΣ modulator for A/D conversion in digital radio

This paper examines the design and implementation of an eighth-order bandpass delta-sigma modulator. The design process is investigated from the signal flow graph level, through to the details of the switched capacitor implementation and layout considerations. Simulation results, highlighting the effects of process variation, are provided and the experimental performance of the modulator described. The modulator is implemented in a 0.8-μm BiCMOS process and occupies an active area of 1.7 mm². Operating from ±2.5-V supplies, the fabricated prototype exhibits stable behaviour and achieves a dynamic range of 67 dB over a 200-kHz bandwidth centered at the commonly used intermediate frequency of 10.7 MHz. This paper, therefore, demonstrates the viability of high-order single-bit bandpass delta-sigma modulation