Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Author

Stojanovic, Vladimir ; Oklobdzija, Vojin G.

Author_Institution

Fac. of Electr. Eng., Belgrade Univ., Serbia

Volume

34

Issue

4

fYear

1999

fDate

4/1/1999 12:00:00 AM

Firstpage

536

Lastpage

548

Abstract

In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications

Keywords

flip-flops; integrated circuit design; low-power electronics; sequential circuits; consistent estimation; design styles; flip-flops; low-power systems; master-slave latches; power budget issues; Capacitance; Circuits; Clocks; Energy consumption; Flip-flops; Frequency estimation; Latches; Master-slave; Power dissipation; Random sequences;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.753687

Filename

753687