A new I-V model considering the impact-ionization effect initiated by the DIGBL current for the intrinsic n-channel poly-Si TFTs

Author

Chen, Hsin-Li ; Wu, Ching-Yuan

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

46

Issue

4

fYear

1999

fDate

4/1/1999 12:00:00 AM

Firstpage

722

Lastpage

728

Abstract

Considering the impact-ionization mechanism occurring in the high drain-bias (V_DS) regime, a new I-V model considering the impact-ionization effect initiated by the drain-induced-grain-barrier-lowering (DIGBL) current has been established for the intrinsic n-channel poly-Si TFT. The simulation results considering the developed impact-ionization current model are in excellent agreement with the experimental output characteristics of the intrinsic n-channel poly-Si TFT with the mask-gate length ranging from 5 μm to 40 μm. In resolving the physical parameters and their underlying operation mechanisms including the grain-barrier height, DIGBL current, and impact-ionization current, the developed I-V model will be beneficial to further understand the underlying physics of the intrinsic poly-Si TFT

Keywords

elemental semiconductors; impact ionisation; semiconductor device models; silicon; thin film transistors; 5 to 40 micron; DIGBL current; I-V model; Si; drain-induced-grain-barrier-lowering; grain-barrier height; high drain-bias regime; impact-ionization current model; impact-ionization effect; intrinsic n-channel poly-Si TFT; mask-gate length; physical parameters; Active matrix liquid crystal displays; Analytical models; Design optimization; Doping; Electric variables; Fabrication; Numerical simulation; Physics; Semiconductor process modeling; Thin film transistors;

fLanguage

English

Journal_Title

Electron Devices, IEEE Transactions on

Publisher

ieee

ISSN

0018-9383

Type

jour

DOI

10.1109/16.753706

Filename

753706