The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters

Physical timing models for small-geometry CMOS inverters with interconnection lines have been developed. Large-signal equivalent circuits of CMOS inverters and 10-section RC ladder networks for interconnection lines are considered assuming nonstep input waveforms and initial delay times. Due to more realistic and complete considerations, the model accuracy is expected to be higher than that of the conventional delay models. Extensive comparisons between model calculations and SPICE simulations show that the models have a maximum relative error of 16% on the delay times of CMOS inverters with interconnection lines of different R and C values and section numbers N and different gate sizes, device parameters, and even input excitation waveforms. Reasonable accuracy, wide applicable range, and high computational efficiency make the timing models quite attractive in MOS VLSI timing verification and autosizing