CMOS current-mode multivalued PLAs

A programmable logic array (PLA) structure for implementation of multivalued combinational and sequential systems is proposed. The PLA is integrable by using a conventional CMOS process and makes a NOR/TSUM two-level implementation of multivalued functions, which can consume less silicon area than an equivalent binary implementation. Pseudo-nMOS and dynamic CMOS implementations for the proposed PLA are also presented, using current-mode inputs and outputs. Since these PLAs operate with several current levels, a significant saving in silicon area can be obtained in comparison with binary PLAs. A four-valued PLA prototype was manufactured using an ordinary CMOS process. Experimental data for this prototype show that the chip operates correctly without significant deterioration in the current levels.