Design of Energy-Efficient High-Speed Links via Forward Error Correction

Author

Narasimha, Rajan ; Shanbhag, Naresh

Author_Institution

Dept. of Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA

Volume

57

Issue

5

fYear

2010

fDate

5/1/2010 12:00:00 AM

Firstpage

359

Lastpage

363

Abstract

In this brief, we show that forward error correction (FEC) can reduce power in high-speed serial links. This is achieved by trading off the FEC coding gain with specifications on transmit swing, analog-to-digital converter (ADC) precision, jitter tolerance, receive amplification, and by enabling higher signal constellations. For a 20-in FR4 link carrying 10-Gb/s data, we demonstrate: 1) an 18-mW/Gb/s savings in the ADC; 2) a 1-mW/Gb/s reduction in transmit driver power; 3) up to 6?? improvement in transmit jitter tolerance; and 4) a 25- to 40-mV improvement in comparator offset tolerance with 3?? smaller swing.

Keywords

analogue-digital conversion; codecs; forward error correction; jitter; ADC; FEC coding; analog-to-digital converter; bit rate 10 Gbit/s; forward error correction; high-speed serial links; jitter tolerance; receive amplification; voltage 25 V to 40 V; Analog-to-digital converter; backplane transceivers; clock jitter; comparative offset; energy-efficiency; forward error correction; high-speed links; transmit driver;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2010.2047318

Filename

5464335