DocumentCode :
1490408
Title :
On via minimization
Author :
Barahona, Francisco
Author_Institution :
Dept. of Combinatorics & Optimization, Waterloo Univ., Ont., Canada
Volume :
37
Issue :
4
fYear :
1990
fDate :
4/1/1990 12:00:00 AM
Firstpage :
527
Lastpage :
530
Abstract :
Minimizing the number of vias in a two-layer circuit is known to reduce to a max cut problem in a planar graph. A similar reduction is presented that makes clear the planarity of the resulting graph. It is shown how to solve this problem in O(n/3/2logn ) time, where n is the number of nodes of the graph. The first polynomial bound obtained for this problem was O(n3 ). Recently different authors also obtained an O(n3/2logn) algorithm; however, they require a graph five times larger than the authors. Known results of polyhedral combinatorics are used to derive a min-max relation. If a heuristic is used, it is shown how to use linear programming duality to derive information about the quality of the heuristic solution
Keywords :
circuit layout; linear programming; minimax techniques; minimisation; network topology; polynomials; heuristic solution; layout design; linear programming duality; max cut problem; min-max relation; planar graph; polyhedral combinatorics; polynomial bound; two-layer circuit; via minimization; Circuits; Combinatorial mathematics; Computational Intelligence Society; Councils; Linear programming; Minimization; Polynomials; Wires;
fLanguage :
English
Journal_Title :
Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0098-4094
Type :
jour
DOI :
10.1109/31.52754
Filename :
52754
Link To Document :
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