Design of an efficient VLSI architecture for 2-D discrete wavelet transforms

Author

Yu, Chu ; Chen, Sao-Jie

Author_Institution

Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan

Volume

45

Issue

1

fYear

1999

fDate

2/1/1999 12:00:00 AM

Firstpage

135

Lastpage

140

Abstract

We present a VLSI architecture for the separable two-dimensional discrete wavelet transform (DWT) decomposition. Using a computation-schedule table, we show how the proposed separable architecture uses only a minimal number of filters to generate all levels of DWT computations in real time. For the computation of an N×N 2-D DWT with a filter length L, this architecture spends around N² clock cycles, and requires 2NL-2N storage units, 3L multipliers, as well as 3(L-1) adders

Keywords

VLSI; digital arithmetic; digital signal processing chips; discrete wavelet transforms; image processing; integrated circuit design; parallel architectures; DWT decomposition; adders; clock cycles; computation-schedule table; efficient VLSI architecture design; filter length; image processing; multipliers; parallel filters; real time computations; separable 2D discrete wavelet transforms; separable architecture; storage units; video processing; Clocks; Computer architecture; Discrete wavelet transforms; Filter bank; Hardware; Signal analysis; Very large scale integration; Video signal processing; Wavelet analysis; Wavelet transforms;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/30.754428

Filename

754428