Title :
Design of an efficient VLSI architecture for 2-D discrete wavelet transforms
Author :
Yu, Chu ; Chen, Sao-Jie
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fDate :
2/1/1999 12:00:00 AM
Abstract :
We present a VLSI architecture for the separable two-dimensional discrete wavelet transform (DWT) decomposition. Using a computation-schedule table, we show how the proposed separable architecture uses only a minimal number of filters to generate all levels of DWT computations in real time. For the computation of an N×N 2-D DWT with a filter length L, this architecture spends around N2 clock cycles, and requires 2NL-2N storage units, 3L multipliers, as well as 3(L-1) adders
Keywords :
VLSI; digital arithmetic; digital signal processing chips; discrete wavelet transforms; image processing; integrated circuit design; parallel architectures; DWT decomposition; adders; clock cycles; computation-schedule table; efficient VLSI architecture design; filter length; image processing; multipliers; parallel filters; real time computations; separable 2D discrete wavelet transforms; separable architecture; storage units; video processing; Clocks; Computer architecture; Discrete wavelet transforms; Filter bank; Hardware; Signal analysis; Very large scale integration; Video signal processing; Wavelet analysis; Wavelet transforms;
Journal_Title :
Consumer Electronics, IEEE Transactions on
