Single Event Test Methodologies and System Error Rate Analysis for Triple Modular Redundant Field Programmable Gate Arrays

Author

Allen, Gregory ; Edmonds, Larry D. ; Swift, Gary ; Carmichael, Carl ; Tseng, ChenWei ; Heldt, Kevin ; Anderson, Scott Arlo ; Coe, Michael

Author_Institution

Jet Propulsion Lab., California Inst. of Technol., Pasadena, CA, USA

Volume

58

Issue

3

fYear

2011

fDate

6/1/2011 12:00:00 AM

Firstpage

1040

Lastpage

1046

Abstract

We present a test methodology for estimating system error rates of Field Programmable Gate Arrays (FPGAs) mitigated with Triple Modular Redundancy (TMR). The test methodology is founded in a mathematical model, which is also presented. Accelerator data from 90 nm Xilinx Military/Aerospace grade FPGA are shown to fit the model. Fault injection (FI) results are discussed and related to the test data. Design implementation and the corresponding impact of multiple bit upset (MBU) are also discussed.

Keywords

field programmable gate arrays; Xilinx Military/Aerospace grade FPGA; fault injection; field programmable gate arrays; mathematical model; multiple bit upset; single event test methodologies; size 90 nm; system error rate analysis; triple modular redundancy; Approximation methods; Error analysis; Field programmable gate arrays; Radiation detectors; Registers; Tunneling magnetoresistance; Error rate calculation; field programmable gate array; single event upset; triple modular redundancy;

fLanguage

English

Journal_Title

Nuclear Science, IEEE Transactions on

Publisher

ieee

ISSN

0018-9499

Type

jour

DOI

10.1109/TNS.2011.2105282

Filename

5746553