DocumentCode
1491528
Title
An Adaptive Equalizer With the Capacitance Multiplication for DisplayPort Main Link in 0.18- 
m CMOS
Author
Lee, Won-Young ; Lee-Sup Kim
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea
Volume
20
Issue
5
fYear
2012
fDate
5/1/2012 12:00:00 AM
Firstpage
964
Lastpage
968
Abstract
An adaptive equalizer with the capacitance multiplication for DisplayPort main link has been proposed. The proposed equalizing filter is based on Miller´s theorem and composed of metal-insulator-metal capacitors and a sub-amplifier. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication. The equalizer satisfies the specification of DisplayPort version 1.1a. The measured eye widths of 2.7 Gb/s data are 0.6 and 0.5 UI for 5 and 8 m cables, respec- tively. The core area is 286 × 380 μm2 and power consumption is 22.3 mW at 2.7 Gb/s at 1.8 V.
Keywords
CMOS analogue integrated circuits; MIM devices; adaptive equalisers; capacitors; CMOS; DisplayPort main link; Miller theorem; active source degeneration capacitor; adaptive equalizer; capacitance multiplication; equalizing filter; metal-insulator-metal capacitors; power 22.3 mW; power consumption; size 0.18 mum; size 5 m; size 8 m; sub-amplifier; voltage 1.8 V; Adaptive equalizers; Capacitance; Gain; MOSFET circuits; Varactors; Adaptive equalizer; DisplayPort; capacitance multiplication;
fLanguage
English
Journal_Title
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher
ieee
ISSN
1063-8210
Type
jour
DOI
10.1109/TVLSI.2011.2130546
Filename
5746557
Link To Document