DocumentCode
1491588
Title
64-bit carry-select adder with reduced area
Author
Kim, Youngjoon ; Kim, Lee-Sup
Author_Institution
Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
Volume
37
Issue
10
fYear
2001
fDate
5/10/2001 12:00:00 AM
Firstpage
614
Lastpage
615
Abstract
A carry-select adder can be implemented by using a single ripple-carry adder and an add-one circuit instead of using dual ripple-carry adders. A multiplexer-based add-one circuit is proposed to reduce the area with negligible speed penalty. The proposed 64 bit carry-select adder requires 42% fewer transistors than the conventional carry-select adder
Keywords
adders; carry logic; multiplexing equipment; 64 bit; carry-select adder; multiplexer-based add-one circuit; ripple-carry adder; speed penalty;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:20010430
Filename
923965
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