DocumentCode :
1492080
Title :
FPGA prototyping of a RISC processor core for embedded applications
Author :
Gschwind, Michael ; Salapura, Valentina ; Maurer, Dietmar
Author_Institution :
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
Volume :
9
Issue :
2
fYear :
2001
fDate :
4/1/2001 12:00:00 AM
Firstpage :
241
Lastpage :
250
Abstract :
Application-specific processors offer an attractive option in the design of embedded systems by providing high performance for a specific application domain. In this work, we describe the use of a reconfigurable processor core based on an RISC architecture as starting point for application-specific processor design. By using a common base instruction set, development cost can be reduced and design space exploration is focused on the application-specific aspects of performance. An important aspect of deploying any new architecture is verification which usually requires lengthy software simulation of a design model. We show how hardware emulation based on programmable logic can be integrated into the hardware/software codesign flow. While previously hardware emulation required massive investment in design effort and special purpose emulators, an emulation approach based on high-density field-programmable gate array (FPGA) devices now makes hardware emulation practical and cost effective for embedded processor designs. To reduce development cost and avoid duplication of design effort, FPGA prototypes and ASIC implementations are derived from a common source: We show how to perform targeted optimizations to fully exploit the capabilities of the target technology while maintaining a common source base.
Keywords :
application specific integrated circuits; embedded systems; field programmable gate arrays; hardware description languages; hardware-software codesign; microprocessor chips; pipeline processing; reconfigurable architectures; reduced instruction set computing; FPGA prototyping; RISC processor core; application-specific processor design; common base instruction set; common source base; design model; design space exploration; development cost; embedded applications; hardware emulation; hardware/software codesign flow; high-density field-programmable gate array; reconfigurable processor core; targeted optimizations; Application specific processors; Computer architecture; Costs; Embedded system; Emulation; Field programmable gate arrays; Hardware; Process design; Prototypes; Reduced instruction set computing;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.924027
Filename :
924027
Link To Document :
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