DocumentCode :
1492115
Title :
Unified functional decomposition via encoding for FPGA technology mapping
Author :
Jiang, Jie-Hong ; Jou, Jing-Yang ; Huang, Juinn-Dar
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
9
Issue :
2
fYear :
2001
fDate :
4/1/2001 12:00:00 AM
Firstpage :
251
Lastpage :
260
Abstract :
Functional decomposition has recently been adopted for look-up table (LUT)-based field-programmable gate array (FPGA) technology mapping with good results. In this paper we propose a novel method to unify functional single-output and multiple-output decomposition. We first address a compatible class encoding algorithm to minimize the number of compatible classes in the image function. After applying the encoding algorithm, we can therefore improve the decomposability in the subsequent decomposition of the image function. The above encoding algorithm is then extended to encode multiple-output functions through the construction of a hyperfunction. Common subexpressions among these multiple-output functions can be extracted during the decomposition of the hyperfunction. Consequently, we can handle multiple-output decomposition in the same manner as single-output decomposition. Experimental results show that our algorithms are promising.
Keywords :
Boolean functions; field programmable gate arrays; logic CAD; logic partitioning; table lookup; FPGA technology mapping; hyperfunction; image function; look-up table; multiple-output decomposition; single-output decomposition; unified functional decomposition; Boolean functions; Data structures; Encoding; Field programmable gate arrays; Image coding; Logic arrays; Partitioning algorithms; Programmable logic arrays; Prototypes; Table lookup;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.924031
Filename :
924031
Link To Document :
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