Title :
An approach to automated hardware/software partitioning using a flexible granularity that is driven by high-level estimation techniques
Author :
Henkel, Jorg ; Ernst, Rolf
Author_Institution :
Comput. & Commun. Res. Lab., NEC Res. Inst., Princeton, NJ, USA
fDate :
4/1/2001 12:00:00 AM
Abstract :
Hardware/software partitioning is a key issue in the design of embedded systems when performance constraints have to be met and chip area and/or power dissipation are critical. For that reason, diverse approaches to automatic hardware/software partitioning have been proposed since the early 1990s. In all approaches so far, the granularity during partitioning is fixed, i.e., either small system parts (e.g., base blocks) or large system parts (e.g., whole functions/processes) can be swapped at once during partitioning in order to find the best hardware/software tradeoff. Since the deployment of a fixed granularity is likely to result in suboptimum solutions, we present the first approach that features a flexible granularity during hardware/software partitioning. Our approach is comprehensive in so far that the estimation techniques, our multigranularity performance estimation technique described here in detail, that control partitioning, are adapted to the flexible partitioning granularity. In addition, our multilevel objective function is described. It allows us to tradeoff various design constraints/goals (performance/hardware area) against each other. As a result, our approach is applicable to a wider range of applications than approaches with a fixed granularity. We also show that our approach is fast and that the obtained hardware/software partitions are much more efficient (in terms of hardware effort, for example) than in cases where a fixed granularity is deployed.
Keywords :
VLSI; embedded systems; hardware-software codesign; high level synthesis; integrated circuit design; logic partitioning; automated hardware/software partitioning; chip area; design constraints; embedded system; flexible granularity; flexible partitioning granularity; hardware effort; high-level estimation techniques; multigranularity performance estimation; performance constraints; power dissipation; suboptimum solutions; Application software; Embedded software; Embedded system; Hardware; National electric code; Power dissipation; Silicon; Software performance; Software systems; System-on-a-chip;
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on