Architecture driven circuit partitioning

Author

Chen, Chau-Shen ; Ting Hwang, Ting ; Liu, C.L.

Author_Institution

Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan

Volume

9

Issue

2

fYear

2001

fDate

4/1/2001 12:00:00 AM

Firstpage

383

Lastpage

389

Abstract

In this paper, we propose an architecture driven partitioning algorithm for netlists with multiterminal nets. Our target architecture is a multifield-programmable gate array (FPGA) emulation system with folded-Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize routability. To that end, we introduce a new cost function: the average number of pseudoterminals per net in a multiway cut. Experimental result shows that our algorithm is very effective in terms of the number of chips used and routability as compared to other methods.

Keywords

field programmable gate arrays; integrated circuit interconnections; logic partitioning; multiterminal networks; network routing; printed circuit layout; architecture driven circuit partitioning; board routing; cost function; emulation system; folded-Clos network; multifield-programmable gate array; multiterminal nets; multiway cut; netlists; pseudoterminals per net; routability; Computer architecture; Emulation; Engines; Field programmable gate arrays; Integrated circuit interconnections; Low power electronics; Partitioning algorithms; Prototypes; Routing; Very large scale integration;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.924060

Filename

924060