DocumentCode :
1492417
Title :
Comments on systematic procedure for test generation of PAL based circuits
Author :
Nale, A.S.
Author_Institution :
Indian Telephone Ind. Ltd., Bangalore, India
Volume :
138
Issue :
2
fYear :
1991
fDate :
3/1/1991 12:00:00 AM
Firstpage :
106
Lastpage :
108
Abstract :
Comments on the test generation algorithm 1 given in a previous paper (see ibid., vol.136, no.2, p.142-9 (1989)), for single S-fault detection are presented. It is shown that the test vectors belonging to the test set generated by algorithm 1 can not detect certain faults. To generate a test set T, detect all single faults in a given PAL modification to the algorithm 1 is suggested. Furthermore, it is shown that some of the conclusions drawn on multiple fault detection capabilities of a single fault test set T discussed in Section 7 of that paper do not hold good in the presence of certain multiple faults with a four way masking cycle.
Keywords :
logic arrays; logic testing; PAL based circuits; four way masking cycle; single S-fault detection; systematic procedure; test generation; test vectors;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
Publisher :
iet
ISSN :
0143-7062
Type :
jour
Filename :
75491
Link To Document :
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