DocumentCode :
1493555
Title :
Board-level partitioning for partial scan using fuzzy logic
Author :
Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ
Volume :
7
Issue :
2
fYear :
1999
fDate :
4/1/1999 12:00:00 AM
Firstpage :
241
Lastpage :
249
Abstract :
We present a board-level partitioning scheme for improved partial scan on the resulting integrated circuits (IC). Fuzzy logic rules and two adaptation techniques allow us to simultaneously minimize four important independent objective functions in the examined problem formulation. The maximum among all sets in the partition are the following quantities: 1) number of scanned nodes in a set; 2) number of incident nets to a set; 3) number of inputs to any set; and finally 4) the period of the global clock. The sets must satisfy upper and lower capacity bounds. We experimented with some ISCAS´89 benchmark circuits and we compared the performance of our tool with four iterative improvement heuristics, each considering only one of the four different functions. Our experimental results indicate that the performance of the proposed tool is very effective
Keywords :
VLSI; boundary scan testing; circuit layout CAD; circuit optimisation; fuzzy logic; integrated circuit layout; integrated circuit testing; logic CAD; logic partitioning; minimisation; printed circuit layout; IC; ISCAS´89 benchmark circuits; board-level partitioning scheme; fuzzy logic; global clock period; independent objective function minimization; integrated circuits; lower capacity bound; partial scan; upper capacity bound; Circuits; Clocks; Computer science; Delay effects; Flip-flops; Fuzzy logic; Manufacturing; Packaging; Pins; Very large scale integration;
fLanguage :
English
Journal_Title :
Fuzzy Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-6706
Type :
jour
DOI :
10.1109/91.755405
Filename :
755405
Link To Document :
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