IBM´s S/390 G5 microprocessor design

Author

Slegel, Timothy J. ; Averill, Robert M., III ; Check, Mark A. ; Giamei, Bruce C. ; Krumm, Barry W. ; Krygowski, Christopher A. ; Li, Wen H. ; Liptay, John S. ; MacDougall, John D. ; McPherson, Thomas J. ; Navarro, Jennifer A. ; Schwarz, Eric M. ; Shum, Ke

Author_Institution

IBM Corp., Poughkeepsie, NY, USA

Volume

19

Issue

2

fYear

1999

Firstpage

12

Lastpage

23

Abstract

The IBM S/390 G5 microprocessor in IBM´s newest CMOS mainframe system provides more than twice the performance of the previous generation, the G4. The G5 system offers improved reliability and availability, along with new architectural features such as support for IEEE floating-point arithmetic and a redesigned L2 cache and processor interconnect. The G5 system implements the ESA/390 instruction-set architecture, which is based on and compatible with the original S/360 architecture. Therefore, it has no RISC (reduced-instruction-set computing) concepts and is one of the most complex of all CISC (complex-instruction-set computing) architectures. Designers had to meet a unique set of challenges to achieve the G5´s level of performance-for example, achieving a very high frequency given the complexity of the architecture

Keywords

CMOS integrated circuits; IBM computers; floating point arithmetic; microprocessor chips; CMOS mainframe system; IBM´s S/390 G5 microprocessor design; IEEE floating-point arithmetic; L2 cache; availability; complex-instruction-set computing; processor interconnect; reliability; Availability; CMOS technology; Computer architecture; Frequency; Integrated circuit interconnections; Logic design; Marine vehicles; Microarchitecture; Microprocessors; Space technology;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.755464

Filename

755464