A self-timed divider using a new fast and robust pipeline scheme

Author

Yang, Jing-ling ; Choy, Chiu-Sing ; Chan, Cheong-Fat

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, China

Volume

36

Issue

6

fYear

2001

fDate

6/1/2001 12:00:00 AM

Firstpage

917

Lastpage

923

Abstract

This paper investigates the potential of self-timed property of differential cascode voltage switch logic (DCVSL) circuits, and examines architectural techniques for achieving self-timing in DCVSL circuits. As a result, a fast and robust handshake scheme for dynamic asynchronous circuit design is proposed. It is novel and more general than other similar schemes. The proposed self-timed datapath scheme is verified by an 8-bit divider which is implemented using AMS 0.6-μm CMOS technology, and the chip size is about 1.66 mm×1.70 mm. The chip testing results show that the divider functions correctly and the latency for 8-bit quotient-digit generation is 17 ns (about 58.8 MHz)

Keywords

CMOS logic circuits; asynchronous circuits; dividing circuits; pipeline arithmetic; 0.6 micron; 17 ns; 8 bit; CMOS technology; asynchronous circuit design; chip size; differential cascode voltage switch logic circuits; handshake scheme; quotient-digit generation; robust pipeline scheme; self-timed datapath scheme; self-timed divider; Asynchronous circuits; CMOS technology; Circuit testing; Delay; Logic circuits; Pipelines; Robustness; Switches; Switching circuits; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.924854

Filename

924854