Enhanced analog “yields” cost-effective systems-on-chip

Author

Tarim, Tuna B. ; Ismail, Mohammed

Author_Institution

Istanbul Tech. Univ., Turkey

Volume

15

Issue

2

fYear

1999

fDate

3/1/1999 12:00:00 AM

Firstpage

12

Lastpage

22

Abstract

As device feature sizes of analog MOS circuits are reduced to the deep-submicron ranges, the effect of process variability on circuit performance and reliability is magnified. Yield is becoming more and more critical and statistical methods are required to simulate the effect of process variability to enable circuit designers to “design-in” quality through circuit robustness. More work is needed particularly in the areas of modeling and statistical CAD of submicron, low-voltage mixed-signal ICs. The characterization work needed to tune models to specific VLSI technology, implementation into the SPICE and APLAC simulators, and use in design and optimization of analog and digital VLSI circuits

Keywords

MOS integrated circuits; SPICE; VLSI; circuit CAD; integrated circuit reliability; low-power electronics; mixed analogue-digital integrated circuits; statistical analysis; APLAC; SPICE; VLSI; analog MOS circuits; circuit performance; circuit robustness; cost-effective systems-on-chip; deep-submicron ranges; device feature sizes; low-voltage mixed-signal ICs; process variability; reliability; statistical CAD; statistical methods; Analog circuits; Design methodology; Design optimization; Fabrication; Integrated circuit reliability; Integrated circuit yield; MOSFETs; Very large scale integration; Voltage; Yield estimation;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.755472

Filename

755472