Test Structure for Characterization of Low-Frequency Noise in CMOS Technologies

This paper describes an alternative way of driving the complementary metal-oxide-semiconductor (CMOS) device into different drain-current levels for low-frequency-noise (LFN) characterization. A floating-gate (FG) test structure that constructs the characterized MOSFET with an extra control gate is proposed. A metal-insulator-metal (MIM) capacitor is used to construct this control gate. Instead of applying different input-dc-bias supplies for the gate terminals of the MOSFETs, the device is directly programmed to the drain-current levels of interest by CHARGE/DISCHARGE operations. In this case, no gate bias is required in the drain-current noise measurement, so that any potential disadvantages from gate-bias supply networks that would prevent accurate noise measurements are totally excluded. The LFN measurement results demonstrating the feasibility of the proposed test structure are also reported.